The present invention relates to a designing apparatus and a designing method for a semiconductor device including a scan flip-flop circuit that can switch between scanning operation and capturing operation, and the semiconductor device.
In order to enable a scanning test of a semiconductor integrated circuit (LSI) as an example of the semiconductor device, a flip-flop circuit (called “FF”) in the circuit is replaced with an FF having a multiplexer (called “MUX”) which is called “scan FF” to switch between a text input and an input of normal operation. The scan FF is configured to operate as a shift register (called “scan chain”) that can be controlled from an external input/output. The scan chain is subjected to the shift operation (called “scan shift operation”) so that an arbitrary test pattern can be set in the respective FFs. The logic of a control signal of the MUX is switched to take in an input from the normal operation (called “capture operation”). A value acquired in the capture operation is again subjected to the shift operation to output a response (called “unload”), and to conduct the application (called “load”) of a subsequent test pattern. Thus, the scan test is conducted. The test pattern to be applied during the scanning operation is in a state substantially close to random. Therefore, in the FF during the scanning operation, a value transits with a probability of about 50%. The transition probability of 50% is considerably higher than that during the normal operation. Also, there is a need to operate all of the FFs during the scanning operation. For that reason, during the scanning test operation, a rate (called “activation rate”) of the circuits causing logic transition as a whole under the influence of the transition of the value of the FF becomes higher, resulting in a tendency to consume an electric power larger than that during the normal operation.
In the FF, there has been known that the result of EX-ORing (exclusive OR) or EX-NORing (exclusive NOR) an output value and an input value, and a clock input are NANDed or ANDed, and when the same value is continuously applied, the clock mask is conducted to reduce the electric power (for example, refer to Japanese Patent Unexamined Application Publication No. Hei-1 (1999)-286609, Japanese Patent Unexamined Application Publication No. Hei-10 (2008)-41789, Japanese Patent Unexamined Application Publication No. Hei-10 (2008)-41789-290143, Japanese Patent Unexamined Application Publication No. 2007-235501, and Japanese Patent Unexamined Application Publication No. 2004-56667).
Also, there has been known a technique in which an output of EX-NORing the present value and an input value in a first latch of a D-type FF, and a clock are ORed, an output of EX-ORing an input value and an output value of a second latch, and a clock are ANDed, and when the same value is continuously input to a D-terminal (input terminal), the clock mask is conducted to reduce a power consumption (for example, Japanese Patent Unexamined Application Publication No. 2004-56667).